DDS Devices Generate High Quality Waveforms: Simple, Efficient and Flexible

Introduction

A key requirement in many industries is to accurately generate, easily manipulate, and quickly change waveforms of different frequencies and types. Whether wideband transceivers require an agile frequency source with low phase noise and excellent spurious-free dynamic performance, or industrial measurement and control systems require stable frequency excitation to quickly, easily, and cost-effectively generate adjustable waveforms while maintaining phase Continuity capability is a critical design criterion, and this is where DDS technology excels.

The task of frequency synthesis
Growing spectrum congestion, coupled with the insatiable demand for lower power and higher quality measurement equipment, are factors that require the use of new frequency ranges and better use of existing frequency ranges.As a result, better control of frequency generation has been sought, in most cases by means offrequency synthesizer. These devices utilize a given frequency, f_Cto generate an associated target frequency (and phase), f_OUT. Its general relation can be simply expressed as:

f_OUT = ε_x× f_C

where the scaling factor ε_xsometimes referred to asnormalized frequency.

This equation is usually implemented using a stepwise approximation algorithm for real numbers. When the scale factor is a rational number, the ratio of two relatively prime numbers (the output frequency and the reference frequency) will be harmonically related. But in most cases, ε_x may belong to a wider set of real numbers, the approximation is truncated once it is within an acceptable range

direct digital frequency synthesis
A practical implementation of a frequency synthesizer isdirect digital frequency synthesis (DDFS), often abbreviated as direct digital synthesis (DDS). This technique utilizes digital data processing to produce a frequency and phase adjustable output that is tied to a fixed frequency reference or clock sourcef_C. related. In the DDS architecture, the reference or system clock frequency is divided by a scale factor that is programmable by a binary tuning word to produce the desired frequency.

In short, a direct digital frequency synthesizer converts a series of clock pulses into an analog waveform, usually a sine, triangle, or square wave. As shown in Figure 1, its main parts are: the phase accumulator (which generates the data of the phase angle of the output waveform), Phase-to-Digital Converter(converting the above phase data to instantaneous output amplitude data), anddigital to analog converter(DAC) (convert this amplitude data to sampled analog data points)

Figure 1. Functional block diagram of the DDS system.

For sine wave output, the phase-to-digital converter is usually a sine look-up table (Figure 2).phase accumulator withNcounts the units and produces a relative to the following equationf_CFrequency of:

in:
Mis the resolution of the tuning word (24 to 48 bits)
Nis the minimum incremental phase change corresponding to the phase accumulator output wordf_Cthe number of pulses.

Figure 2. Typical DDS architecture and signal path (with DAC).

due to changesNchanges the output phase and frequency immediately, so the system itself hasPhase Continuity, characteristic, which is one of the key attributes of many applications.No loop settling time is required, unlike analog systems such as locksphase ring (PLL).

A DAC is usually a high-performance circuit designed specifically for the DDS core (phase accumulator and phase-amplitude converter). In most cases, the resulting device (usually a single chip) is generally referred to as pure DDS or C-DDS.

Practical DDS devices generally integrate multiple registers to implement different frequency and phase modulation schemes. Like a phase register, its stored phase content is added to the output phase of the phase accumulator. In this way, the phase of the output sine wave can be delayed corresponding to one phase tuning word. This is useful for communications system phase modulation applications. The resolution of the adder circuit determines the number of bits in the phase tuning word and, therefore, the resolution of the delay.

Integrating a DDS engine and a DAC on a single device has both advantages and disadvantages, but, whether integrated or not, a DAC is required to produce a high-quality analog signal with exceptional purity. The DAC converts the digital sine output to an analog sine wave, which may be single-ended or differential. Some key requirements are low phase noise, excellent wideband (WB) and narrowband (NB)Spurious free dynamic range (SFDR) and low power consumption. In the case of an external device, the DAC must be fast enough to process the signal, so devices with built-in parallel ports are very common.

DDS and other solutions
Other methods of generating frequencies include analogphase locked loop(PLL), clock generator and dynamic programming of the output of the DAC using the FPGA.These technologies can be easily compared by looking at spectral performance and power consumption, and Table 1 presents the results in a qualitative manner

Table 1. DDS vs. Competing Technologies – High-Level Comparison

A phase-locked loop is a feedback loop whose components are: aphase comparatora divider and aVoltage Controlled Oscillator (VCO). The phase comparator compares the reference frequency to the output frequency (usually the output frequencyN) to compare. The error voltage produced by the phase comparator is used to adjust the VCO and thus the output frequency. When the loop is established, the output will maintain an accurate relationship in frequency and/or phase to the reference frequency. PLLs have long been recognized as low phase noise and highSpurious free dynamic range Ideal for (SFDR) applications.

The inability of PLLs to tune frequency outputs and waveforms precisely and quickly and their slow response limit their applicability for fast frequency hopping and partial frequency shift keying and phase shift keying applications.

Other options, including integrated DDS engineField Programmable Gate Array (FPGAs) – Combined with off-the-shelf DACs to synthesize output sine waves – Although it can solve the PLL frequency hopping problem, it also has its own shortcomings. Major system drawbacks include higher operating and interface power requirements, higher cost, larger size, and additional software, hardware, and memory issues that system developers must consider. For example, using the DDS engine option in modern FPGAs, to generate a 10 MHz output signal with a dynamic range of 60 dB requires up to 72 kB of memory space. In addition, designers need to accept and become familiar with the subtle trade-offs and architecture of the DDS core. .

From a practical point of view (see Table 2), DDS technology has enabled unprecedented low power consumption, spectral performance and cost level. While pure DDS products are unlikely to match the performance and design flexibility of high-end DAC technology combined with FPGAs, the advantages of DDS in size, power, cost and simplicity make it the first choice for many applications.

Table 2. Benchmark Analysis Summary – Frequency Generation Techniques (<50 MHz)

	phase locked loop	DAC + FPGA	DDS
Spectral performance	high	high	middle
System Power Requirements	high	high	Low
digital frequency tuning	none	Yes	Yes
Tuning response time	high	Low	Low
Solution size	middle	high	Low
Waveform flexibility	Low	middle	high
cost	middle	high	Low
Design reuse	middle	Low	high
implementation complexity	middle	high	Low

It should also be pointed out that because DDS devices are fundamentally digitally generating output waveforms, they can simplify the architecture of some solutions or allow for digital programming of waveforms. Although a sine wave is often used to explain the function and operation of a DDS, a triangular or square wave (clock) output can also be easily generated with modern DDS ICs, thus eliminating the look-up table of the former case and the DAC of the latter case necessary because it is sufficient to integrate a simple and accurate comparator.

DDS Capabilities and Limitations
Image and envelope: Sin(x)xx roll off
The actual output of the DAC is not a continuous sine wave, but a series of pulses with a sinusoidal time envelope. The corresponding spectrum is a series of images and aliased signals. Image along sin(x)/x Envelope distribution (see |Amplitude| plot in Figure 3). Filtering is necessary to reject frequencies outside the band of interest, but not high-order aliasing that occurs in the passband (for example, due to DAC nonlinearity)

Nyquist criterion It is required that at least two sample points are required per cycle to reconstruct the desired output waveform.The image response occurs at the sampled output frequencyK f_CLOCK × f_OUT. In this example, where f_CLOCK = 25 25 MHz and f_OUT = 5 MHz, the first and second image frequencies appear at (see Figure 3)f_CLOCK × f_OUT, o is 20 MHz and 30 MHz. The third and fourth image frequencies appear at 45 MHz and 55 MHz. Note that sin(x)/xZero values ​​occur at multiples of the sampling frequency.whenf_OUT more than theNyquist bandwidth (1/2 f_CLOCK), the first image frequency will appear within the Nyquist bandwidth and aliasing will occur (for example, a 15 MHz signal will alias down to 10 MHz).Cannot use traditional NyquistAnti-aliasingfilter to remove aliased images from the output

Figure 3. Sin(x)/x roll-off in DDS.

In a typical DDS application, a low-pass filter is used to suppress the effects of the image response in the output spectrum.In order to keep the cutoff frequency requirement of the low-pass filter reasonable and to keep the filter design simple, a feasible approach is to use an economical low-pass output filter tof_OUT Bandwidth is limited tof_CLOCKabout 40% of the frequency.

The magnitude of any given image frequency relative to the fundamental can be calculated using the sin(x)/x formula. Since the function rolls off with frequency, the magnitude of the fundamental output will decrease inversely proportional to the output frequency; in a DDS system, the decrease is –3.92 dB over the DC-Nyquist bandwidth range.

The magnitude of the first image frequency is large—within 3 dB of the fundamental.To simplify the filtering requirements for DDS applications, a frequency plan must be developed and the image frequency and sin(x)/x magnitude responses analyzed atf_OUTandf_CLOCKSpectrum requirements at the target frequency. The online interactive design tool supports the ADI DDS product family, quickly and easily simulates the magnitude of the image frequency, and allows the user to select frequencies where the image lies outside the band of interest.For more useful information, seeMore information and useful linkspart.

Other unwanted frequencies in the output spectrum, such as the DAC’s integral and differential linearity errors, DAC-related surge energy, and clock feedthrough noise, do not follow sin(x)/xroll-off response. These unwanted frequencies will appear in many places in the output spectrum as harmonics and spurious energy – but typically their magnitudes will be much lower than the image response. The general noise floor of a DDS device is determined by the cumulative combination of substrate noise, thermal noise effects, ground coupling, and coupling from other signal sources. The noise floor, performance spurs, and jitter of a DDS device are profoundly affected by board layout, power supply quality, and—most importantly—input reference clock quality.

jitter
The edges of a perfect clock source will occur at precise time intervals that never change. Of course, this is impossible; even the best oscillators are made of suboptimal components, with defects such as noise. A good quality low phase noise crystal oscillator has picosecond jitter accumulated over millions of clock edges. Factors that cause jitter include thermal noise, oscillator circuit instability, and external disturbances from power, ground, and output connections, all of which can interfere with the oscillator’s timing characteristics. Additionally, oscillators are affected by external magnetic or electric fields as well as radio frequency interference from nearby transmitters. In oscillator circuits, a simple amplifier, inverter, or buffer can also introduce additional jitter to the signal.

Therefore, it is critical to choose a stable reference clock oscillator with low jitter and steep edges.A higher frequency reference clock allows greater oversampling, and, byfrequency divisionJitter can be mitigated to some extent because dividing the signal will produce the same amount of jitter over a longer period of time, thus reducing the percentage of jitter on the signal.

Noise – including phase noise
The noise of a sampling system depends on many factors, the first being reference clock jitter, which appears as phase noise on the fundamental signal. In DDS systems, truncating the phase register output can introduce systematic errors that vary from code to code. Binary words do not cause truncation errors. But for non-binary words, phase noise truncation errors can create spurs in the spectrum. The frequency/magnitude of the spur depends on the codeword. The quantization and linearity errors of the DAC can also introduce harmonic noise into the system. Time domain errors such as undershoot/overshoot and code errors can add to the distortion of the output signal.

application
DDS applications can be divided into two categories:

• Communications and radar systems requiring agile frequency sources for data encoding and modulation applications
• Measurement, industrial, and optical applications requiring general-purpose frequency synthesis capabilities and programmable tuning, sweeping, and excitation capabilities

In both cases, there is a trend towards higher spectral purity (lower phase noise and higher spurious-free dynamic range), along with requirements for low power consumption and small size to accommodate long-range or Requirements for battery powered equipment.

DDS in modulation/data coding and synchronization
DDS products first appeared in radar and military applications, and the development of some of their characteristics (increased performance, cost, size, etc.) has made DDS technology increasingly popular in modulation and data encoding applications.This section will discuss two data encoding schemes and how they are implemented in DDS systems

binary frequency shift keying (BFSK, or simplyFSK) is one of the simplest forms of data encoding. The transmission mode of data is to make the frequency of a continuous carrier change between two discrete frequencies (one is binary 1, that is, mark, and the other is binary 0, that is, space). Figure 4 shows the relationship between the data and the transmitted signal.

Figure 4. Binary FSK modulation.

Binary 1s and 0s are represented as two different frequencies, f0 and f1, respectively. This encoding scheme can be easily implemented in DDS devices. The DDS frequency tuning word representing the output frequency is changed to generate f0 and f1 from the ones and zeros to be transmitted. There are at least two devices in ADI’s pure DDS product family, AD9834 and AD9838 (see also appendix), the user can simply program the two current FSK frequency tuning words into the IC’s embedded frequency registers. To change the output frequency, a dedicated pin FSELECT must be used to select the register containing the corresponding tuning word (see Figure 5)

Figure 5. FSK encoding using the tuning word selector of the AD9834 or AD9838 DDS.

Phase Shift Keying (PSK) is another simple form of data encoding. In PSK, the frequency of the carrier remains the same, and information is conveyed by changing the phase of the transmitted signal. PSK can be implemented using a variety of schemes. The simplest method, often called binary PSK (ie BPSK), uses only two signal phases: 0° (logic 1) and 180° (logic 0). The status of each bit depends on the status of the previous bit. If the phase of the wave does not change, the signal state will remain the same (low or high). If the phase of the wave changes by 180°, i.e. the phase is reversed, the signal state will change (low to high, or high to low). PSK encoding can be easily implemented in DDS products because most devices have a separate input register (phase register) that can be loaded with phase values. This value is added directly to the phase of the carrier without changing its frequency. Changing the contents of this register modulates the phase of the carrier, resulting in a PSK output. For applications requiring high-speed modulation, the AD9834 and AD9838, with built-in phase register pairs, allow the signal on their PSELECT pin to alternate between preloaded phase registers to modulate the carrier as needed.

More complex PSKs employ four or eight wave phases. In this way, the transmission rate of binary data will be higher than that of BPSK modulation whenever the phase changes. In four-phase modulation (Orthogonal PSK), the possible phase angles are 0°, +90°, −90°, and +180°; each phase transition may represent two signal factors The AD9830, AD9831, AD9832, and AD9835 provide four phase registers, By continuously updating the registers with different phase offsets, complex phase modulation schemes can be implemented.

Utilize multiple DDS elements for I/Q functions in synchronous mode
Many applications require the generation of two or more sine or square wave signals with a known phase relationship. A common example is in-phase and quadrature modulation (I/Q), a technique in which signal information is obtained from the carrier frequency at 0° and 90° phase angles. Two separate DDS elements can be run with the same source clock to output a signal whose phase relationship can be directly controlled and manipulated. In Figure 6, the AD9838 device is programmed with a reference clock; the same RESET pin is used to update both devices.In this way, simple I/Q modulation can be achieved

RESET must be initialized after power-up and before transferring any data to the DDS. As a result, the DDS output can be placed into a known phase, making it a common reference angle for synchronizing multiple DDS devices. When new data is sent to multiple DDS devices at the same time, the relative phase relationship between DDSs can be maintained, or the relative phase offset between multiple DDSs can be adjusted predictively through the phase offset register. The AD983x family of DDS products has 12-bit phase resolution with an effective resolution of 0.1°.

Figure 6. Synchronizing two DDS elements.

For more information on synchronizing multiple DDS devices, see application note AN-605 Synchronizing Multiple DDS-Based Frequency Synthesizers AD9852.

network analysis
Many applications in the Electronic world require the collection and decoding of data from networks, such as analog measurements and optical communication systems. Normally, a system analysis requirement is to simulate a circuit or system at a frequency of known magnitude and phase, and to analyze the characteristics of the response signal passing through the system.

The information collected on the response signals is used to determine critical system information. The scope of test networks (see Figure 7) can be very broad, including cable integrity testing, biomedical sensing, and flow rate measurement systems. Whenever the basic requirement is to generate a frequency-based signal and compare the phase and amplitude of the response signal to the original signal, or to excite a range of frequencies through the system, or to have different phase relationships (such as having an I/Q function) system), the direct digital frequency synthesis IC can be used to digitally control the excitation frequency and phase through software conveniently and elegantly.

Figure 7. Typical network analysis architecture using frequency excitation.

Cable Integrity/Loss Measurements
Cable Integrity Measurement is a non-intrusive cable analysis method widely used in applications such as aircraft wiring, local area networks (LANs), and telephone lines. One way to determine performance is to see how much signal is lost through the cable. By injecting a signal of known frequency and amplitude, the user can measure the amplitude and phase at the far end of the cable, thereby calculating cable attenuation. Parameters such as DC resistance and characteristic impedance will affect the attenuation of a specific cable. The result is usually expressed in decibels (0 dB) below the source over the entire test frequency range. The target frequency depends on the cable type. DDS devices can be used as excitations with the necessary frequency resolution due to their ability to generate a wide range of frequencies.

Flowmeter
A related application is flow analysis of water, other liquids and gases in pipes. An example is ultrasonic flow measurement, which works on the principle of phase shift, as shown in Figure 8. Basically, a signal is emitted from one end of the channel where the liquid is flowing, while a sensor is placed at the other end to measure the phase response (depending on the flow rate). There are many variations of this technique. The test frequency depends on the substance being measured; in general, the output signal tends to be emitted over a range of frequencies. DDS has the flexibility to seamlessly set up and change frequency

Figure 8. Ultrasonic flow meter.

More information and useful links
Interactive Design Tools
What is it? It is an online interactive design tool for DDS, an aid for selecting tuning words given a reference clock and target output frequency and/or phase. The tool’s programming calculations give the tuning word and other configuration bits used when programming the device’s serial interface. After applying an external reconstruction filter, the ideal output harmonics of the selected reference clock and output frequency can be displayed. Links to ADI Design Tools can be found on the Interactive Design Tools home page The AD9834 Design Tool is one example.

Evaluation Kit
The AD983x family comes with a full-featured evaluation kit complete with schematics and layout guidelines. With the software provided in the evaluation kit, the user can easily program, configure and test the device (see Figure 9)

Figure 9. AD9838 evaluation software interface.

Other useful DDS signals can be found on the DDS website.

See also:

Murphy, Eva and Colm Slattery. “A Complete Guide to Direct Digital Synthesis.” Ask The Applications Engineer—33. Application Engineer Q&A – 33. Simulate a conversation. 2004 Vol. 38 No. 3: 8–12.

Digital Signal Synthesis Technology Tutorial. 1999. Analog Devices, Inc. (Return to DDS Performance)

appendix
AD9838 Introduction:The functional block diagram of the AD9838 DDS is shown in Figure 10. Manufactured in a fine-line CMOS process, the device is an ultra-low power (11 mW) pure DDS. The 28-bit frequency register supports 0.06 Hz frequency resolution and 16 MHz clock, and 0.02 Hz frequency resolution and 5 MHz clock. Phase and frequency modulation are configured by software or pin selection through on-chip registers. The device features −68 dBc wideband and −97 dBc narrowband SFDR and operates over the extended –40°C to +125°C temperature range. The device is available in a small 4 mm × 4 mm, 20-lead LFCSP (Lead Frame Chip Scale) package.

Figure 10. Functional block diagram of the AD9838 DDS.