[Introduction]Today, the third-generation semiconductor technology represented by GaN and SiC is gaining momentum. Compared with conventional semiconductor materials, GaN and SiC have large band gaps, high breakdown electric field strength, high electron mobility, high thermal conductivity, low dielectric constant, strong radiation resistance…so higher power can be achieved Density, higher voltage driving capability, faster switching frequency, higher efficiency, better thermal performance, smaller size, in high temperature, high frequency, high power, high radiation and other power Electronic applications A strong impact on traditional silicon-based IGBT and MOSFET devices.
In this boom in third-generation semiconductor technology, GaN has shown higher growth than SiC. According to the forecast of Yole Development, the global GaN power device market will rapidly climb from US$46 million in 2020 to US$1.1 billion in 2026, with an average compound annual growth rate of 70%!
The reason for such a high acceleration is the successful penetration of GaN devices into the smartphone fast charger market from 2020 onwards. However, in addition to this, the rather “likeable” characteristics of GaN devices themselves are the more fundamental reasons.
Advantages of GaN
Due to their different characteristics, GaN and SiC have clear application market segments in power electronics: SiC devices can provide voltage levels up to 1,200V and have high current-carrying capabilities, so they are used in automotive and locomotive traction inverters, high-power It has obvious advantages in applications such as solar power stations and large-scale three-phase grid converters; while the voltage level of GaN devices is usually around 600V, but it has higher switching quality and supports higher switching frequencies, making it ideal for applications below 10kW Therefore, it has a wide range of applications, covering consumer electronics, communications and industrial AC and DC power supplies, electric vehicle on-board chargers, power adapters, servo drive power stages and other products.
In the market below 10kW, although SiC devices are also involved, the advantages of GaN are more prominent in the following three aspects.
First, there is no PN junction in the lateral structure used by GaN FETs, so there is no body diode and its associated reverse recovery process; while there is a body diode in SiC FETs, a reverse recovery process is required when switching, which brings Additional reverse recovery losses and time affect switching power dissipation and speed. In other words, in applications below 10kW, GaN has better switching quality and can operate at higher switching frequencies, which also makes it possible to use smaller peripheral components.
Figure 1: Application areas of different power electronics
(Image source: TI)
Second, SiC devices need to use more expensive substrate materials and dedicated manufacturing processes, which will increase the overall cost of their applications; while GaN devices can be made based on standard Si substrates, there is greater room for subsequent cost reductions. Comprehensive evaluation, GaN will be more advantageous over time in terms of total cost of ownership.
Figure 2: Cost trends for different FET technologies
(Image source: TI)
Furthermore, since the manufacturing process of GaN devices is highly compatible with the traditional Si semiconductor process, it is possible to do more articles in the same device package, such as integrating the driver and GaN FET, and adding other more This will undoubtedly be of great benefit to improving system performance, optimizing design, and reducing system costs.
Integrated drive
Traditional GaN device application systems are composed of discrete GaN FETs and driver ICs, because GaN FETs and drivers are manufactured using different process technologies, and sometimes devices from different suppliers are required. However, this discrete architecture presents challenges when faced with high slew rate switching applications due to the parasitic inductance of the bond wires and leads interconnecting between different device packages and devices, which can cause Switching losses, ringing and reliability issues.
To eliminate these problems caused by parasitic inductance, an effective solution is to integrate the GaN FET and driver in one package to greatly reduce the parasitic inductance.
Figure 3 compares the GaN FET and driver discrete package architecture with a single package set approach. The latter will provide further performance improvements for the entire system. We will do further analysis below.
Figure 3: Comparison of GaN FET and driver discrete architecture (a) and integrated package (b) options (Image source: TI)
Common source inductance
Due to the high switching rate of GaN FETs, the influence of the parasitic factor of common source inductance has to be considered. In Figure 3a, Lcs is the common source inductance. In a traditional TO-220 discrete package, the source and wire of the GaN FET flow from the bonding wire to the lead, where both the sink current and the gate current flow. The slew rate is limited when the common source inductance, including bond wires and package leads, is above 10nH, and lower slew rates mean longer transition times, which in turn result in higher cross-conduction losses, increasing the overall switching losses.
However, if the integrated package in Figure 3b is used, the ground of the driver is directly soldered to the source pad of the GaN FET die, which greatly shortens the common source inductance path shared by the power loop and the gate loop, making the GaN device The ability to switch at a higher current slew rate reduces switching losses.
Gate loop inductance
The gate loop inductance includes gate inductance and driver ground inductance, which has a huge impact on switching performance. When the GaN FET is turned off, the gate is pulled down by a resistor that is low enough to not turn back on during switching due to the drain being pulled high. This resistor forms an LRC tank with the gate capacitance and gate loop inductance of the GaN device. When the gate loop inductance value is large, its quality factor Q will increase, resulting in higher ringing, which significantly Increased stress on GaN FET gates – Be aware that overstress on FET gates can adversely affect reliability.
Gate loop inductance also affects turn-off retention. When the gate of the low-tube device is held at the off voltage and the high-tube is on, the low-tube drain capacitance delivers a large current into the gate’s hold loop, this current diverts the gate VGS through the gate loop inductance Push up, thereby increasing the shoot-through current, and the increase in the shoot-through current will lead to an increase in cross-conduction energy loss. And you’ll find that reducing gate stress and enhancing device turn-off retention are difficult to achieve when the gate loop inductance is high.
Integrated packaging of GaN FET+ drivers is clearly a good way to reduce gate loop inductance. As can be seen from Figure 3, in the discrete architecture (Figure 3a), the gate inductance includes the driver output bonding wire Ldrv_out, the GaN gate bonding wire Lg_gan and the PCB trace Lg_pcb, and the inductance value is usually from a few nH to more than 10 nH; and if It is an integrated package (Figure 3b), the gate inductance can be controlled below 1nH, which provides a guarantee for the overall optimization of system performance.
Protection function support
To ensure safe and reliable operation of GaN FETs, protection features are essential. For example, over-temperature protection can turn off the GaN FET when it senses that the temperature exceeds the protection threshold. When the GaN FET and the driver are integrated in one package, due to the good thermal conductivity of the lead frame, it can ensure that the temperature of the two is relatively close, making the thermal protection design simpler and more efficient.
Current protection of GaN requires a low-inductance connection between the GaN device and the driver because of the additional inductance in the interconnect that can cause ringing and longer the blanking time to prevent the current protection from failing. The integrated package solution just reduces the interconnect inductance, allowing the current protection circuit to react as quickly as possible when needed.
To summarize, when we integrate GaN FET and driver in a single package, we can eliminate common source inductance and achieve high current slew rate; we can also reduce gate loop inductance, reduce gate stress during turn-off and improve device At the same time, it also helps to support the realization of efficient and reliable protection functions such as overheating, overcurrent and overvoltage, which can be said to serve multiple purposes!
TI’s GaN power stages
The LMG341x series of GaN power stage devices from Texas Instruments (TI) use the integrated package of “GaN FET + driver”, and also integrate a wealth of protection functions, allowing developers to take full advantage of the advantages of GaN devices to achieve Design for higher power density and higher efficiency power electronics applications.
Taking the LMG341xR150 in this series as an example, compared with traditional silicon MOSFETs, it has ultra-low input and output capacitance values, zero reverse recovery characteristics can reduce switching losses by 80%, and achieve lower EMI and Switch node ringing, these advantages make it an ideal solution for high-density, high-efficiency topology designs such as totem-pole PFCs.
Figure 4: System block diagram of the LMG341xR150
(Image source: TI)
The device achieves zero common-source inductance due to the integrated gate driver, and a propagation delay of 20ns ensures that it operates at MHz-level frequencies and switches at 100V/ns (user-adjustable slew from 25V/ns to 100V/ns Vds ringing at almost zero rate), so the LMG341xR150 can be used as an alternative to traditional cascode GaN and discrete GaN FET architectures, greatly improving power supply performance and reliability, and greatly simplifying design.
Figure 5: LMG341xR150 switching performance at 100V/ns
(Image source: TI)
The LMG341xR150 also provides robust protection features including overcurrent protection (less than 100ns response time and greater than 150V/ns slew rate immunity), transient overvoltage immunity, thermal protection, and UVLO protection and self-monitoring capabilities eliminate the need for external protection components, simplifying design complexity and reducing system cost.
Needless to say. The promotion and application of GaN technology has provided a huge impetus for the upgrade of power electronic products. However, in order to give full play to the advantages of GaN, in addition to improving the “carving” of the GaN device itself, it is also necessary to fully consider the influencing factors of the entire power supply system. It turns out that integrating the driver and GaN FET in one package is an effective solution for optimization from a system perspective, which can improve the performance of the GaN power system while making the entire design process faster!
If you encounter bottlenecks when building a solution with discrete GaN devices, you might as well try the LMG341xR150 integrated solution of “GaN FET + driver + protection function”, there will be many “surprises” waiting for you !
Source: Mouser Electronics
The Links: BT42008VSS-122 DMC-40218-CEM