2021-06-15

On-Chip Electrostatic Discharge Protection for ICs

Semiconductor chips are susceptible to high current and high voltage phenomena. To achieve component-level protection, we employ on-chip ESD protection circuits to provide a safe ESD current discharge path.

Electrostatic discharge (ESD) is a frequent menace to electronics. During an ESD event, an amount of charge is transferred from one object to another, e.g., from a person to an integrated circuit (IC). This charge transfer can result in a very high current passing through the IC within a brief period, damaging the device if it cannot dissipate the energy quickly.

ESD can hit the devices throughout the product lifetime, during manufacturing and assembly, by the end-user, or in maintenance.

The rapid evolution and availability of emerging technologies, like mobile devices, automotive electronics, industrial and medical applications, create unique needs for on-chip protection against ESD stresses.

ESD protection is mandatory for electronic components, and its design is of prime concern in the semiconductor industry. For a reliable operation, the ESD protection should be considered both at the component level as well as the device level.

 

ESD Components Tests (ESD Models)

A set of standards document the ESD qualification tests to guarantee the reliability and certify the systems and components. They specify the testing procedure, test equipment calibration, and routine verification.

This section addresses the component-level tests. Passing these tests is a prerequisite to obtaining the certifications of a product and bringing it to market.

The models or tests for ESD events that may take place in components in daily life – each representing a particular physical phenomenon – are:

  • The human body model
  • The machine model 
  • The charged device model 
  • The transmission line pulse testing 

 

The Human Body Model

The human body model (HBM) happens when a charged person touches a component with a finger. Initially developed for the mining industry, this is the oldest ESD test – it simulates the transfer of charge from a finger to an integrated circuit pin with other pins grounded. 

Recent data shows that HBM seldom emulates actual ESD events. Latest-generation package styles are regularly too small for people to handle with their fingers, and the  manufacturing process for most large components employs automated equipment, so people hardly touch the components.

Figure 1 shows the HBM pulse waveform.

 

On-Chip Electrostatic Discharge Protection for ICs
Figure 1. Example of HBM pulse waveform. Image based on S. H. Voldman, 2012.

 

The Machine Model Pulse

The machine model (MM) pulse is developed to model an ESD event where a charged metal object touches an IC pin. Figure 2 shows the MM pulse waveform.

 

On-Chip Electrostatic Discharge Protection for ICs
Figure 2. Example of MM pulse waveform. Image based on S. H. Voldman, 2012.

 

In the HBM and MM models, the charge is transferred to the component.

 

The Charged Device Model

The charged device model (CDM) occurs when a charged device contacts a grounded object. In this testing method, the component is the charge source, and it discharges through a grounded body. 

The CDM model replicates in-house and customer IC failures at the component level. It determines an IC’s vulnerability to an ESD event where a charged package discharges through a grounded metal object. Currently, such discharge events are the leading cause of ESD failures in modern circuits.

Figure 3 shows the CDM current waveform.

 

On-Chip Electrostatic Discharge Protection for ICs
Figure 3. Example of CDM current waveform.

 

The Transmission Line Pulse

In the transmission line pulse testing (TLP), a voltage source charges a transmission line cable and then the system discharges a series of ESD-like pulses into the device under test. It evaluates the device performance operating under an ESD stress. 

This testing method is an equivalent or a substitute for the HBM methodology and can also measure or characterize the ESD performance.

Figure 4 shows the TLP pulse waveform.

 

On-Chip Electrostatic Discharge Protection for ICs
Figure 4. Example of TLP pulse waveform. Image based on S. H. Voldman, 2012.

 

Common ESD Failures

ESD failures are disastrous and can lead to instant malfunction of IC chips.

Junctions and oxides are prone to damages. The basic mechanisms for ESD induced failure are:

  • Junction burnout in silicon: This is the most common HBM failure mechanism – the injection of an ESD transient of energy can drive the junction into a breakdown.
  • Oxide breakdown: Another major category of ESD damage arises when a high voltage applied across the oxide layer – high-voltage overstress – causes the dielectric to breakdown. As the dielectric breaks down, it starts conducting current. The heat from the current flow can produce hot spots and melt down the dielectric, silicon, and other materials.
  • Metallization burnout: This produces openings in the interconnection paths. It happens when the temperature – the I²R heat – reaches the material’s melting point. It is commonly a secondary effect, occurring after junction or oxide failure.

 

On-Chip ESD Protection Devices

On-chip ESD protection structures protect the input, output, and power supply pins of the core circuit by providing a safe ESD discharge path to the ground bus/rail. These protection structures are off during the regular system operation but turn on swiftly in the presence of an ESD event, discharging the surge current to the ground.

During the event, the protection circuitry clamp the pins to a low voltage. They return to the off-state after discharging the current. The ESD event must not damage the device.

When on-chip protection is not possible due to the technology limitations, off-chip protection solutions – located in cables, connectors, ceramic carriers, or circuit boards – are useful. In some cases, custom solutions designed with optimized approaches may cut costs.

An ESD protection device should comply with four characteristics:

  1. Robustness
  2. Effectiveness
  3. Speed
  4. Transparency

In addition to being robust and effective, the ESD protection circuitry should be fast enough to turn on before the main circuit that is being protected. Moreover, the protection circuitry must be transparent and must not alter the performance of the main circuit

 

Building Blocks of ESD Circuits

There are different techniques to build protection clamps. Their choice depends on the technology and design restrictions. Three devices commonly used as the ESD protection devices are:

  1. Diodes
  2. Grounded gate N-channel MOSFET
  3. Silicon-controlled rectifier 

 

The Diode

Diodes have the simplest structure and meet the requirements for low-voltage ESD applications when forward-biased. Operating under this condition, they are one of the best ESD protection elements – exhibit low turn-on voltage, low on-resistance, and handle high ESD currents. 

Under reverse bias, diodes show high turn-on voltage, high on-resistance, and low current handling capability, making them unsatisfactory ESD protection devices. A downside is the increased leakage current.

 

Grounded gate N-channel MOSFET 

Grounded-gate n-channel MOSFETs (GGNMOS) are commonly used to protect CMOS-based designs against ESD events. These devices have a structure and operation similar to that of normal MOS; however, they employ different layout techniques to have optimized performance as an ESD protection device. 

A GGNMOS device can operate in either active  or snapback mode of operation. In the active mode of operation, it functions as a standard NMOS device. The snapback effect allows the passage of large currents at low voltages – a high-voltage ESD event triggers the current flow; however, this current flow continues with a low voltage across the ESD protection device. Snapback is the most common mode of operation. A disadvantage is its low robustness.

 

Silicon-Controlled Rectifier

The silicon-controlled rectifier (SCR) is the most efficient ESD protection device in terms of its high robustness, owing to its bipolar conduction mechanism. 

A drawback is its tendency to latch-up – conduction of current after the ESD event ends. With the right design, they can provide outstanding ESD performance at a tolerable latch-up risk.

Note that while diodes are non-snapback-type devices, SCRs and GGNMOSs have snapback characteristics.

 

On-Chip ESD Protection Strategy

The ESD protection strategy consists of clamping the overstress voltages and using on-chip protection structures to provide a discharge path for ESD currents.

The on-chip ESD protection circuits are included to protect the input, output, and power pads against ESD events.

These protection elements remain passive during regular operation of the protected device and activate only in the presence of an ESD pulse – by detecting the rise time and the overvoltage. When an ESD pulse is detected, the protection circuitry will provide a safe discharge path for the ESD current.

Figure 5 shows a typical design where the ESD protection circuits are added to the input, output, and power terminals

 

On-Chip Electrostatic Discharge Protection for ICs
Figure 5. On-chip ESD protection circuits. Image from M.D. Ker, 1999.

 

This network consists of the following protection components:

  • Input pad to the ground (Vss)
  • Input pad to power rail (Vdd)
  • Output pad to the ground (Vss)
  • Output pad to power rail (Vdd)
  • Power rail (Vdd) to the ground (Vss)

The ESD protection techniques are employed with all significant processes, including CMOS, BiCMOS, and III-V compounds.

 

A Review of Grounding ICs 

The electrostatic discharge (ESD) phenomenon occurs due to a transfer of electrostatic charges between two objects with different electric potentials; it damages the ICs due to the substantial and quick dissipation of energy.

The ESD protection methods shunt the ESD currents through a safe discharge path, dissipate the energy in the ESD devices, and clamp the voltages at a safe level.

ESD failure becomes a more severe reliability concern as semiconductor dimensions shrink to upgrade its performance.

It is critical to verify the ESD immunity and the reliability of a circuit design. The significant component level standards are the human body model (HBM), the machine model (MM), and the charged device model (CDM).

Common failures associated with ESD are junction burnout, oxide breakdown, and metallization burnout.

Examples of ESD protection devices are diodes, GGNMOS, and SCR devices.

On-chip ESD protection devices protect internal circuits against ESD damage. Voltage clamping devices are off under normal conditions but carry current after reaching their threshold voltage.